1. Field of Invention
The field of invention relates generally to the computing sciences and more specifically to a prefetch with request for ownership without data.
2. Background
FIG. 1 shows a processor 100 having a plurality of processor cores 101_1 to 101_N. Each of the cores has its own respective L1 cache 102_1 to 102_N but shares a common system memory 103. The collective goal of the L1 caches 102_1 to 102_N is to minimize accesses to the shared memory 103 by keeping a data item in the cache of a core that is apt to operate on it. However, as it is entirely possible that the respective program code running on the different cores 101_1 to 101_N may wish to concurrently operate on a same item of data, a “coherency” protocol is implemented to ensure that an item of data remains “consistent” within the computing system as a whole.
A commonly used coherency protocol is the MESI protocol. The MESI protocol assigns one of four different states to any cached item: 1) Modified (M); 2) Exclusive (E); 3) Shared (S); and, 4) Invalid. A cache line in the M state corresponds to a “dirty” cache line that includes recent, updated data that has not yet been updated to shared memory. A cache line in the E state corresponds to data that is “clean”. That is, its data content is the same as its corresponding entry (i.e., same address) in shared memory. When a processor writes new data to a cache line in the E state, the state of the cache line is changed to the M state. When a cache line is in the M state, the updated data must be written back to shared memory before a read of shared memory is permitted at the cache line's corresponding address. The write back to memory causes the cache line to transition from the M state to the E state.
A cache line in the S state typically corresponds to a cache line having multiple copies across the various caches 102_1 to 102_N. In a typical situation, a single instance of a cache line is resident in the E state in the cache of a particular processor. If another processor desires the same cache line, a second copy of the cache line is sent to the requesting processor. The state of the cache line therefore changes from E to S as there are now two copies of the cache line in the system. Other aspects of the MESI protocol exist. However such features are well know and need not be discussed here.
If any of the processors 101_1 to 101_N desires to write to a copy of a cache line in the S state, the processor that desires to perform the write issues a request for ownership (RFO) for the cache line that is broadcast to the other processors. If the RFO is granted, any other copies of the cache line in the caches of the other processors are invalidated (i.e., change from the S to I state).
If the processor that was grated the RFO has a local copy of the cache line in the S state, the grant of the RFO transitions the state of the local copy to the E state, and, the subsequent write changes the state again from the E state to the M state. If the processor that was granted the RFO did not have a local copy of the cache line when the RFO was issued, as part of the grant of the RFO it is provided with a copy of the cache line from one of the other processors that has a copy. The cache line is initially held in the E state. The subsequent write transitions the cache line from the E state to the M state.
When a processor issues an RFO for a cache line that it desires to write to but does not currently have a copy of in its own cache, there is no guarantee that the desired cache line is in any of the other caches. In this case, where no instance of the desired cache line exists in any of the other caches, the cache line is fetched from shared memory and provided to the requesting processor's cache in the E state.